Intra-die variation contributes to the loss of matched behavior between structures on the same chip. Controlling over the intra-die variation has been an important element for the successful manufacture of integrated circuits (IC). Generally, a major source of an intra-die variation can be wafer-level position dependent. For example, a wafer scale variation can result in trends that are reflected across the spatial range of the chips, e.g., a concentric ring pattern in thickness from the center of the wafer outwards. Another major source of an intra-die variation can be die-pattern dependent. For example, intra-die variation can be caused by a photolithography process (e.g., variations in a mask, distortion in lens of an exposure system, loading uniformity in an etching system, etc.). For another example, a variation of film thickness caused by a nonuniformity in a deposition system and/or a chemical-mechanical planarization (CMP) process could also contribute to the intra-die variation. These variations in physical dimensions of devices on the same chip could result in a variation in performance, such as variations in leakage current, threshold voltage, resistance, and delay within devices on the same chip.
Particularly, resistance variation in conductive patterns (e.g., polycrystalline silicon gate) caused by the intra-die variation may result in differences in supply voltages on gates, affect temperature profile caused by heating, and increase uncertainty in timing (e.g., inaccuracy in delay). Therefore, a resistance variation of conductive patterns needs to be minimized. Besides the aforementioned process variations which can contribute to this effect, processes that have short time scales, e.g., rapid thermal annealing (RTA) process widely used for annealing materials at a high ramp rate and for a short period of time, can also contribute to the resistance variation. Since the length scale over which thermal equilibrium can be reached for a given time is a function of thermal conductivity and specific heat of materials, device structure and layout pattern design therefore have great impact to the local thermal equilibrium. For example, the resistance variation of doped polycrystalline silicon patterns on the same chip has a correlation with the pattern density (i.e., area of polycrystalline silicon patter per unit area), which is primarily due to the difference of reflectance of incident RTA lamp spectrum. Despite this long felt need to control the RTA induced intra-die resistance variation, no suitable methods are available.